
2009 Microchip Technology Inc.
DS39687E-page 25
PIC18F2XJXX/4XJXX FAMILY
FOSC<2:0>
Oscillator Selection bits
111 = EC+PLL (S/W controlled by PLLEN bit), CLKO on RA6
110 = EC oscillator (PLL always disabled) with CLKO on RA6
101 = HS+PLL (S/W controlled by PLLEN bit)
100 = HS oscillator (PLL always disabled)
011 = INTOSCPLLO, internal oscillator with PLL (S/W controlled by PLLEN bit), CLKO
on RA6, port function on RA7
010 = INTOSCPLL, internal oscillator with PLL (S/W controlled by PLLEN bit), port
function on RA6 and RA7
001 = INTOSCO, internal oscillator, INTOSC or INTRC (PLL always disabled), CLKO on
RA6, port function on RA7
000 = INTOSC, internal oscillator INTOSC or INTRC (PLL always disabled), port function
on RA6 and RA7
WDTPS<3:0>
CONFIG2H(1,2) Watchdog Timer Postscale Select bits 1111 = 1:32,768
1110 = 1:16,384
1101 = 1:8,192
1100 = 1:4,096
1011 = 1:2,048
1010 = 1:1,024
1001 = 1:512
1000 = 1:256
0111 = 1:128
0110 = 1:64
0101 = 1:32
0100 = 1:16
0011 = 1:8
0010 = 1:4
0001 = 1:2
0000 = 1:1
DSWTPS<3:0>
CONFIG3L
Deep Sleep Watchdog Timer Postscale Select bits
The DSWDT prescaler is 32; this creates an approximate base time unit of 1 ms.
1111 = 1:2,147,483,648 (25.7 days)
1110 = 1:536,870,912 (6.4 days)
1101 = 1:134,217,728 (38.5 hours)
1100 = 1:33,554,432 (9.6 hours)
1011 = 1:8,388,608 (2.4 hours)
1010 = 1:2,097,152 (36 minutes)
1001 = 1:524,288 (9 minutes)
1000 = 1:131,072 (135 seconds)
0111 = 1:32,768 (34 seconds)
0110 = 1:8,192 (8.5 seconds)
0101 = 1:2,048 (2.1 seconds)
0100 = 1:512 (528 ms)
0011 = 1:128 (132 ms)
0010 = 1:32 (33 ms)
0001 = 1:8 (8.3 ms)
0000 = 1:2 (2.1 ms)
DSWDTEN
CONFIG3L
Deep Sleep Watchdog Timer Enable bit
1 = DSWDT enabled
0 = DSWDT disabled
DSBOREN
CONFIG3L
Deep Sleep BOR Enable bit
1 = BOR enabled in Deep Sleep
0 = BOR disabled in Deep Sleep (does not affect operation in non Deep Sleep modes)
TABLE 5-7:
PIC18F47J13 AND PIC18F47J53 FAMILY DEVICES: BIT DESCRIPTIONS (CONTINUED)
Bit Name
Configuration
Words
Description
Note 1: The Configuration bits can only be programmed indirectly by programming the Flash Configuration Word.
2: The Configuration bits are reset to ‘1’ only on VDD Reset; it is reloaded with the programmed value at any device Reset.
3: These bits are not implemented in PIC18F47J13 family devices.
4: Once this bit is cleared, all the Configuration registers which reside in the last page are also protected. To disable code
protection, perform an ICSP Bulk Erase operation.
5: Not implemented on PIC18F47J53 family devices.